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XCR3384XL: 384 Macrocell CPLD
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DS024 (v1.7) August 21, 2003
Preliminary Product Specification
Features
* * * * * Low power 3.3V 384 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 135 MHz 384 macrocells with 9,000 usable gates Available in small footprint packages - 144-pin TQFP (118 user I/O) - 208-pin PQFP (172 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (220 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero PowerTM (FZP) CMOS design technology - 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O) Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 clocks available per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for additional I/O 2.7V to 3.6V supply voltage at industrial grade voltage range Programmable slew rate control per output Security bit prevents unauthorized access Refer to XPLA3 family data sheet (DS012) for architecture description
Description
The XCR3384XL is a 3.3V, 384 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 24 function blocks provide 9,000 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 135 MHz.
TotalCMOS Design Technique for Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3384XL TotalCMOS CPLD (data taken with 24 resetable up/down, 16-bit counters at 3.3V, 25C).
280 240 200 160 120 80 40 0 0 20 40 60 80 100 120 140
DS024_01_061802
*
*
* * * * * *
Typical ICC (mA)
Frequency (MHz)
Figure 1: XCR3384XL Typical ICC vs. Frequency at VCC = 3.3V, 25C Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25C Frequency (MHz) Typical ICC (mA) 0 0.02 1 2.2 10 24.4 20 42.4 40 82.6 60 123.0 80 155.6 100 187.8 120 227.5 140 258.1
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DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD
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DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol VOH
(2)
Parameter Output High voltage
Test Conditions VCC = 3.0V to 3.6V, IOH = -8 mA VCC = 2.7V to 3.0V, IOH = -8 mA IOH = -500 A
Min. 2.4 2.0 90% VCC(3) -10 -10 -
Max. 0.4 10 10 100 5 140 8 12 10
Unit V V V V A A A mA mA pF pF pF
VOL IIL IIH ICCSB ICC CIN CCLK CI/O
Output Low voltage Input leakage current I/O High-Z leakage current Standby current Dynamic current(4,5) capacitance(6)
IOL = 8 mA VIN = GND or VCC to 5.5V VIN = GND or VCC to 5.5V VCC = 3.6V f = 1 MHz f = 50 MHz
Input pin
f = 1 MHz f = 1 MHz f = 1 MHz
Clock input capacitance(6) I/O pin capacitance (6)
Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating conditions 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. See Table 1, Figure 1 for typical values. 5. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing. 6. Typical values, not tested.
100 90 80 70 60 IOL (3.3V)
mA
50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (2.7V) IOH (3.3V)
Volts
DS012_10_031802
Figure 2: Typical I/V Curve for the XPLA3 Family, 25C
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DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
-7 Symbol TPD1 TPD2 TCO TSUF TSU1(4) TSU2 TH
(4) (4) (4)
-10 Max. 7.0 7.5 4.5 20 20 135 200 200 9.0 9.0 8.0 9.0 Min. 3.0 5.5 6.5 0 4.0 6.0 Max. 9.0 10.0 5.8 20 20 102 200 200 11.0 11.0 10.3 11.0 Min. 3.0 6.7 7.9 0 5.0 7.5 -
-12 Max. 10.8 12.0 6.9 20 20 83 200 200 13.0 13.0 12.4 13.0 Unit ns ns ns ns ns ns ns ns ns ns ns MHz s s ns ns ns ns
Parameter Propagation delay time (single p-term) Propagation delay time (OR array)(3) Clock to output (global synchronous pin clock) Setup time(fast input register) Setup time (single p-term) Setup time (OR array) Hold time Global Clock pulse width (High or Low) P-term clock pulse width Input rise time Input fall time
Min. 2.5 4.3 4.8 0 3.0 4.5 -
TWLH TR TL
(4)
TtPLH
(4)
fSYSTEM TINIT(4) TPOE
(4) (4) (4)
(4)
Maximum system frequency Configuration time(5) ISP initialization time P-term OE to output enabled P-term OE to output disabled(6) P-term clock to output P-term set/reset to output valid
TCONFIG(4)
TPOD TPCO TPAO
(4)
Notes: 1. Specifications measured with one output switching. 2. See XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 13 mA at 3.6V. 6. Output CL = 5 pF.
DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD
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Internal Timing Parameters(1,2)
-7 Symbol
Buffer Delays
-10 Max. Min. Max. Min.
-12 Max. Unit
Parameter
Min.
TIN TFIN TGCK TOUT TEN TLDI TSUI THI TECSU TECHO TCOI TAOI TRAI TPTCK TLOGI1 TLOGI2 TF TLOGI3 TUDA TSLEW
Input buffer delay Fast input buffer delay Global clock buffer delay Output buffer delay Output buffer enable/disable delay
-
2.5 2.7 1.0 2.5 4.5
-
3.3 3.3 1.3 3.2 5.2
-
4.0 3.3 1.5 3.8 6.0
ns ns ns ns ns
Internal Register and Combinatorial Delays
Latch transparent delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output delay Register async. S/R to output delay Register async. recovery Product term clock delay Internal logic delay (single p-term) Internal logic delay (PLA OR term)
0.8 0.3 2.0 3.0 -
1.3 1.0 2.0 5.0 2.0 2.0 2.5
1.0 0.5 2.5 4.5 -
1.6 1.3 2.0 7.0 2.5 2.5 3.5
1.2 0.7 3.0 5.5 -
2.0 1.6 2.2 8.0 3.0 3.0 4.2
ns ns ns ns ns ns ns ns ns ns ns
Feedback Delays
ZIA delay
-
3.1
-
4.0
-
5.0
ns
Time Adders
Fold-back NAND delay Universal delay Slew rate limited delay
-
2.0 2.2 4.0
-
2.5 2.8 5.0
-
3.0 3.5 6.0
ns ns ns
Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See XPLA3 family data sheet (DS012) for timing model.
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DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD
Switching Characteristics
VCC
S1 Component R1 R2 C1 VOUT R2 C1 Values 390 390 35 pF
R1 VIN
Measurement TPOE (High) TPOE (Low) TP
S1 Open Closed Closed
S2 Closed Open Closed
S2
Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH - 300 mV.
DS023_03_102401
Figure 3: AC Load Circuit
7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 6.4 6.3 6.2 6.1 6.0 1 2 4 8 16
+3.0V 90%
(ns)
10% 0V
TR
1.5 ns
TL
1.5 ns
Number of Adjacent Outputs Switching 3.3V, 25C
DS024_04_061802
Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
DS017_05_042800
Figure 4: Derating Curve for TPD2
Figure 5: Voltage Waveform
DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD
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Pin Descriptions
Table 2: XCR3384XL User I/O Pins TQ144(1) Total User I/O Pins 118 PQ208 172 FT256 212 FG324 220
Table 3: XCR3384XL I/O Pins (Continued) Function MacroBlock cell TQ144(1) PQ208 3 3 3 3 3 3 3 3 FT256 E15 F13 E16 F14 F15 G12 G15 G13 F16 E14 D16 F12 C16 E13 D15 D14 B16 C15 G14 FG324 G22 H20 H21 J19 J21 J22 K19 K21 K22 G21 G19 F22 F21 F20 E22 E21 F19 E20 L19 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 90 89 88 87 104 106 107 110 111 112 113 114 116 86(1,2) 84 22 24 25 26 27 28 4 3 207 206 205 204 203 29 30(2) 31 FT256 G16 H13 H12 H15 H14 H16 J14 A16 E12 C14 D13 A15 B15 B14 C13 J15 J13(2) J16 L14 K15 FG324 L20 L21 M20 M19 M22 N22 N21 N19 D22 C22 B21 B20 C19 B19 A20 C18 B18 P22 P20(2) P19 R22 R21 -
Notes: 1. XCR3384XL TQ144 JTAG pins are not compatible with other members of the XPLA3 family in the TQ144 package.
Table 3: XCR3384XL I/O Pins Function MacroBlock cell TQ144(1) PQ208 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 94 93 92 91 96 97 98 99 100 101 102 103 13 15 16 17 18 19 20 12 11 10 9 8 7 6 21
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DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD Table 3: XCR3384XL I/O Pins (Continued) FG324 R20 T22 T21 T20 AA16 Y16 W16 AB17 AA17 AB18 AA18 W17 AA19 T19 U22 U21 U20 V22 U19 V21 V20 W22 Y18 AA20 Y19 AA21 Y20 Function MacroBlock cell TQ144(1) PQ208 8 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 74 122 121(1,2) 120 131(1,2) 132 133 48 47 46 45 187 188 189(2) 190 192 193 194 178 177 176(2) 175 173 172 FT256 N14 R16 M13 P15 D9 A9 C10(2) A10 D10 B11 C11 B12 E10 B8 D8 A7(2) C8 C7 B7 D7 C10 D10 A9 FG324 Y21 W20 W21 Y22 C13 D13 B14(2) C14 D14 A15 B15 C15 A16 B11 C11 D11(2) A10 B10 -
Table 3: XCR3384XL I/O Pins (Continued) Function MacroBlock cell TQ144(1) PQ208 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 83 82 81 67 68 69 80 79 78 77 75 70 71 72 33 34 35 36 62 61 60 59 58 57 56 37 38 39 40 42 43 44 55 51 49 FT256 K14 K16 K13 L15 R13 M11 T14 N12 R14 P13 T15 P14 T16 K12 L16 M15 N15 L13 M16 M14 N16 L12 M12 R15 N13 P16
DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD Table 3: XCR3384XL I/O Pins (Continued) Function MacroBlock cell TQ144(1) PQ208 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 134 117 118 119 139 138 137 136 61 62 63 171 202 201 199 198 197 196 195 163 164 166 167 168 169 170 70 69 68 67 66 FT256 A6 A14 E11 A13 D12 B13 C12 A12 D11 A11 E6 A4 C5 B5 D6 A5 C6 B6 E7 N10 P11 M10 R11 T12 FG324 B9 A19 D17 A18 C17 B17 A17 D16 C16 B16 D7 C7 B7 A7 C8 B8 A8 D9 C9 W13 AB14 AA14 Y14 W14 Table 3: XCR3384XL I/O Pins (Continued) Function MacroBlock cell TQ144(1) PQ208 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 65 66 47 46 45 44 43 60 56 55 54 48 65 64 91 92 93 95 96 97 98 71 73 76 77 78 79 80 90 89 88 FT256 R12 N11 T13 P12 R6 M7 T5 T6 R5 N6 T4 P5 R4 T11 R10 P10 T10 N9 R9 P9 T9 N7 T7 P6 FG324 AB15 AA15 Y15 AB16 AA8 Y8 AB7 AA7 Y7 W7 AB6 AA6 Y6 Y13 AA13 AB13 W12 AA12 AB12 Y11 AA11 W11 AB8 W9 Y9
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DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD Table 3: XCR3384XL I/O Pins (Continued) FG324 AA9 AB9 W10 Y10 AA10 AB11 E2 F3 F4 D1 D2 E3 C2 B2 D3 E1 F2 G4 G3 G2 H3 Function MacroBlock cell TQ144(1) PQ208 18 18 18 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 21 21 21 21 21 21 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 11 12 143 142 141 140 14 15 16 18 42 41 141 140 139 155 156 158 159 160 161 162 138 137 136 135 133 132 131 99 100 101 102 103 FT256 E2 F3 F2 C3 D4 A2 A1 B3 C4 A3 D5 B4 G4 G1 G3 H1 H4 G2 H3 J1 J3 M6 T3 N5 R3 P4 FG324 H2 H1 J4 C4 B4 C5 B5 A4 D6 A5 C6 B6 J3 J2 K4 K3 K2 K1 L4 L3 L2 AB5 W6 AB4 AA5 Y5 -
Table 3: XCR3384XL I/O Pins (Continued) Function MacroBlock cell TQ144(1) PQ208 16 16 16 16 16 16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 18 18 18 18 18 18 18 18 18 18 18 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 49 53 6 5 4 2 1 7 8 9 10 87 86 84 81 147 148 149 150 151 153 154 146 145 144 142 FT256 R7 P7 T8 N8 R8 P8 E4 D1 F5 C2 D3 C1 B1 B2 D2 E3 E1 F4 F1 G5
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XCR3384XL: 384 Macrocell CPLD Table 3: XCR3384XL I/O Pins (Continued) Function MacroBlock cell TQ144(1) PQ208 21 21 21 21 21 21 21 21 21 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 24 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 40 39 38 37 19 20 21 22(1,2) 23 25 36 35 26 104 106 130 129 128 127(2) 126 124 123 108 109 110 111 112 113 114 122 FT256 T2 R2 N4 H2 J5 J2 J4 K1(2) K3 K2 L1 M5 P2 P3 T1 N3 R1 M4 P1 L5 K4 FG324 AA4 AB3 Y4 AA3 M2 M3 M4 N1 N2(2) N3 N4 P1 P2 AA2 Y3 Y2 W3 W2 W1 V3 U4 V2 P3 Table 3: XCR3384XL I/O Pins (Continued) Function MacroBlock cell TQ144(1) PQ208 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 27 28 29 30 31 32 34 121 120 119 118 117 115 FT256 L3 K5 M1 L2 M2 L4 M3 N2 FG324 P4 R1 R2 R3 T2 T3 U2 U3
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Notes: 1. XCR3384XL TQ144 JTAG pins are not compatible with other members of the XPLA3 family in the TQ144 package. 2. JTAG pins.
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DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD
Table 4: XCR3384XL Global, JTAG, Port Enable, Power, and No Connect Pins Pin Type IN0 / CLK0 IN1 / CLK1 IN2 / CLK2 IN3 / CLK3 TCK TDI TDO TMS PORT_EN VCC TQ144(1) 128 127 126 125 86(1) 131(1) 121(1) 22(1) 33(2) 24, 50, 51, 58, 73, 76, 95, 115, 123, 130, 144 PQ208 181 182 183 184 30 176 189 127 116(2) 5, 23, 41, 63, 74, 83, 85, 107, 125,143, 165, 179, 186, 191 FT256 B9 A8 C9 B10 J13 A7 C10 K1 N1(2) E8, E9, F7, F8, F9, F10, G6, G11, H5, H6, H11, J6, J11, J12, K6, K11, L7, L8, L9, L10, M8, M9 FG324 C12 B12 D12 A12 P20 D11 B14 N2 T4(2) A11, A13, D8, D15, H4, H19, J10, J11, J12, J13, K9, K14, L9, L14, M1, M9, M14, N9, N14, N20, P10, P11, P12, P13, R4, R19, W8, W15, Y12, AB10 D4, D5, D18, D19, E4, E19, J9, J14, K10, K11, K12, K13, L10, L11, L12, L13, M10, M11, M12, M13, N10, N11, N12, N13, P9, P14, V4, V19, W4, W5, W18, W19 A1, A2, A3, A6, A14, A21, A22, B1, B3, B13, B22, C1, C3, C20, C21, D20, D21, F1, G1, G20, H22, J1, J20, K20, L1, L22, M21, P21, T1, U1, V1, Y1, Y17, AA1, AA22, AB1, AB2, AB19, AB20, AB21, AB22
GND
3, 13, 17, 52, 57, 59, 64, 85, 105, 124, 129, 135,
14, 32, 50, 72, 75, 82, 94, 134, 152, 174, 180, 185, 200
E5, F6, F11, G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10, L6, L11
No Connects
108, 109
1, 2, 52, 53, 54, 105, 157, 208
-
Notes: 1. XCR3384XL TQ144 JTAG pins are not compatible with other members of the XPLA3 family in the TQ144 package. 2. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for full explanation.
DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD
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Device Part Marking and Ordering Combination Information
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Device Type Package Speed Operating Range
XCRxxxxXL TQ144 7C
This line not related to device part number
1
Sample package with part marking.
Device Ordering and Part Marking Number XCR3384XL-7TQ144C XCR3384XL-7PQ208C XCR3384XL-7FT256C XCR3384XL-7FG324C XCR3384XL-10TQ144C XCR3384XL-10PQ208C XCR3384XL-10FT256C XCR3384XL-10FG324C XCR3384XL-10TQ144I XCR3384XL-10PQ208I XCR3384XL-10FT256I XCR3384XL-10FG324I XCR3384XL-12TQ144C XCR3384XL-12PQ208C XCR3384XL-12FT256C XCR3384XL-12FG324C XCR3384XL-12TQ144I XCR3384XL-12PQ208I XCR3384XL-12FT256I XCR3384XL-12FG324I
Speed (pin-to-pin delay) 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 12 ns 12 ns 12 ns 12 ns 12 ns 12 ns 12 ns 12 ns
Pkg. Symbol TQ144 PQ208 FT256 FG324 TQ144 PQ208 FT256 FG324 TQ144 PQ208 FT256 FG324 TQ144 PQ208 FT256 FG324 TQ144 PQ208 FT256 FG324
No. of Pins 144-pin 208-pin 256-ball 324-ball 144-pin 208-pin 256-ball 324-ball 144-pin 208-pin 256-ball 324-ball 144-pin 208-pin 256-ball 324-ball 144-pin 208-pin 256-ball 324-ball
Package Type Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP) Fine-Pitch BGA (FT) Fineline BGA Package (FG) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP) Fine-Pitch BGA (FT) Fineline BGA Package (FG) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP) Fine-Pitch BGA (FT) Fineline BGA Package (FG) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP) Fine-Pitch BGA (FT) Fineline BGA Package (FG) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP) Fine-Pitch BGA (FT) Fineline BGA Package (FG)
Operating Range(1) C C C C C C C C I I I I C C C C I I I I
Notes: 1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = -40 to +85C
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DS024 (v1.7) August 21, 2003 Preliminary Product Specification
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XCR3384XL: 384 Macrocell CPLD
Revision History
The following table shows the revision history for this document Date 02/08/01 04/11/01 Version 1.0 1.1 Initial Xilinx release. Update TSUF spec to meet UMC characterization data. Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec. Added 324-ball Fineline BGA pinouts and package. Updated Typical I/V curve, Figure 2: added voltage levels. Updated AC Electrical Characterisitics; Internal Timing Parameters; added TQ144 package and pinouts. Updated TSUF spec to match software timing. Added single p-term setup time (TSU1) to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated TINIT spec and TCONFIG spec. Updated THI spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for TPOD delay measurement. Changed TQ144 pinout for pins 34 and 35. Changed to Preliminary, updated AC and DC specs per characterization review. Updated Note 5 on AC Specifications from 10 mA to 13 mA at 3.6V. Updated TPCO (added TPTCK). Updated Ordering Information format. Updated test conditions for IIL and IIH. Updated Package Device Marking Pin 1 orientation. Revision
04/19/01 08/10/01 01/08/02
1.2 1.3 1.4
01/06/03
1.5
07/15/03 08/21/03
1.6 1.7
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